I provide two constraint checkers in addition to the diode.Constraints.fwd and diode.Constraints.ts_fwd checkers of my base class: rds, and vt.

Instance Variable mp An instance of mosfet_model.MOSFET_Physics.
Instance Variable Rds_on Minimum on-state resistance.
Instance Variable Vgs_Rds_on Vgs at Rds_on.
Instance Variable VT_max The maximum allowable value of VT.
Method __init__ Undocumented
Method rds Ensures that rd + rs is less than Rds_on, since the Ohmic extrinsic resistances don't even account for the accumulation region and fully inverted channel.
Method vt Ensures that the threshold voltage isn't too high to not allow inversion at the lowest Vgs value of setup 211.

Inherited from Constraints:

Instance Variable IV_fwd_max Maximum forward-bias current and voltage to be considered.
Instance Variable R_lead Lead resistance (each).
Instance Variable Tj_min Minimum operating temperature (deg C).
Method fwd Forward-bias voltage as determined by the diode equation must be no less than 1/2 and no more than 2x what is expected at maximum specified current.
Method ts_fwd Denominator of current source expression simulating temp-sensitive Rs must be > 0 even at coldest rated temp of Tj_min:
mp =
An instance of mosfet_model.MOSFET_Physics.
Rds_on =
Minimum on-state resistance.
Vgs_Rds_on =
Vgs at Rds_on.
VT_max =
The maximum allowable value of VT.
def __init__(self, *args, **kw):
Undocumented
def rds(self, p):

Ensures that rd + rs is less than Rds_on, since the Ohmic extrinsic resistances don't even account for the accumulation region and fully inverted channel.

Also keeps rs from being larger than rd. In reality, it should be considerably smaller. Not only do electrons have to travel much farther in the drift region for rd, but the light doping there (<10% of NA in p+ region) makes its resistivity much higher than that of the p+ source region for rs. The fact that it has more cross-sectional area than the source region does not compensate much for those two factors.

Zheng Yang ("Power MOSFET," ECE442 handout) has VDMOS source plus source contact resistivity at 0.06 mOhm/cm^2, with most of that being from the contact, and drift plus substrate plus drain contact (all part of rd) being 0.41 mOhm/cm^2. (That doesn't include accumulation resistance he puts at 0.66 mOhm/cm^2 and JFET resistance at 0.19 mOhm/cm^2.) This corresponds to an rs/rd ratio of about 15%.

For UMOS, Zheng Yang has source plus contact at 0.0505 mOhm/cm^2, with the source part vanishingly small. Drift plus substrate drain contact is 0.27 mOhm/cm^2 (not including accumulation resistance he puts at 0.055 mOhm/cm^2). This corresponds to an rs/rd ratio of about 19%.

def vt(self, p):

Ensures that the threshold voltage isn't too high to not allow inversion at the lowest Vgs value of setup 211.

Assumes 1e+18 for polysilicon gate doping.

TODO: Account for eta. Maybe do Vt calculation the same way MOS3 does.

API Documentation for pingspice, generated by pydoctor at 2021-09-18 08:41:11.