Defines fundamental parameter AV objects:

• m_L: Channel length (m).
• m_L2xj: Multiplier to go from channel length m_L to junction depth. T&M p. 257.
• m_L2W: Multiplier to go from channel length to width. Power MOSFETs can have literally meters of channel width inside the package, in the form of thousands of strips (e.g., ST Microelectronics's StripFET), repeated honeycomb structures (e.g., Infinion's HexFET), or conventional VDMOS cells. Narrow-channel effects are not modeled, so there's no need to separate out individual cell widths, if there is even such a structure in the device.
• m_tox: Oxide thickness (m).
• m_Bt: Coefficient of Vgst/tox in denominator of effective channel mobility equation. T&M (p. 220) introduce this term as Beta_sub_theta and suggest its range is "typically 0.5 to 2 nm * V^-1." A value of zero would entirely eliminate the effect of higher Vgs reducing mu.
• m_vsa: Fitting factor for modest adjustment of maximum carrier velocity. "Most MOSFET models allow the value of |vd|max, and/or that of the 'critical field' Ec, to be chosen for best fit of model predictions to measured drain current values. The reason for this is that these parameters are difficult to measure. Also, in MOS transistor work, these theories are often applied in a simplified manner anyway, and this fact can be compensated to some degree by choosing parameter values for best fit with measurements" (T&M p. 246).
• m_kappa: Fitting factor for channel length modulation. The MOS3 model multiplies excess Vds (over Vds_sat), then calculates the hypotenuse of that with a voltage of some kind (?) that is expected at the nominal pinchoff point. T.H.Lee (2001), p. 27.
• {m_NA}: The acceptor concentration (doping atoms per cm^3), of the P+ substrate (bulk).

With tempsens enabled for temperature sensitivity, the following are also defined, in channel:

• T_chm: Scaling of channel mobility temperature dependence relative to non-saturated theoretical with 1.5 power.
• T_chv: Coefficient for linear threshold voltage decrease with higher temperature.

With an LDD, two more temperature sensitivity parameters are also defined, T_drm and T_drs. See drift_region.

Makes a voltage source mv_vacc for an accumulation effect on the drift. Add to 1.0 to form the denominator of a variable drift resistance. Here's a schematic view of what happens:

           +-------------------------------+
           |       Accumulation part       |
   17 >--->|>>+>>>>>>>>>>>>>>>>>>>>>>>>>+>>|>----> 18
           |  |     of drift region     |  |
           +--|-------------------------|--+
              |                         |
              |  +------+     +------+  |
              +->|-     |     |     -|<-+
                 | Diff |-+ +-| Diff |
             +-->|+     | | | |     +|<--+
             |   +------+ | | +------+   |
             |            | |            |
   291 >-----+------------|-|------------+
                          | |
                          V V
                        +-----+    +----------+
                        | Avg |--->| -V(m_aV) |---+
                        +-----+    +----------+   |
                                                  |
                          +--<---- mv_vgat ---<---+
                          |
                          |     +--------------+
                          +---->| V(m_aK)*()^2 |---> mv_vacc
                                +--------------+

Increases from 0.0 with m_aK times the square of increasing gate voltage relative to accumulation region midpoint after threshold m_aV is reached.

For PMOS, the (negative) gate voltage relative to accumulation region midpoint is inverted. So, with the slightly negative drain voltage (relative to source) of a P-channel MOSFET in strong inversion, making the gate voltage more negative causes mv_vacc to increase, just as it would with more positive gate voltage gets the more positive internally.

Makes a B-source producing reverse current from node nfrom to nto to counteract current approaching or exceeding the saturation current limit defined by max-current node nmc.

Note that this does not reduce the current flowing through the semiconductor region. Instead, it makes the region's resistance (between node nfrom and nto) appear higher by limiting the net current flow between those terminals. The node nto is named because current goes "to" the current-limiting circuitry, and gets pulled "from" it at node nfrom.

For PMOS, nfrom and nto are simply reversed, internally. The call to this method remains the same. You will have to reverse your shunt, however.

Pre-limited current is measured through zero-valued voltage source with name shunt.

Here's how it works (direction of current flow for NMOS):

             +---------+
   nto --+-->|+ shunt -|>--------------+
         |   +---------+               |
         |        |                    |
         ^        |                    |
         |        x                    |
         |   +----------+              V
         +--<|- B:Isat +|<--+   +---------------+
             +----------+   |   |               |
                  x x       |   | Semiconductor |
                  | |       |   |  region       |
   nmc -----------+ |       ^   |               |
                    |       |   +---------------+
   Tj --------------+       |          V
                            |          |
   nfrom <------------------+----<-----+

When current through shunt is much lower than maximum, as defined by the voltage at node nmc, B:Isat produces very little reverse current. As the shunt current approaches maximum, the reverse current through B:sat increases to more fully counteract the shunt current. The limit of the reverse current is the forward current minus the saturation current. Thus the upper limit of effective current flow is the saturation current.

If temperature sensitivity is enabled, makes a voltage source that reduces the voltage at nmc with higher temperature and uses that as the current limit.

Returns an expression for the relative current in a parallel current path implementing temperature sensitivity of semiconductor mobility, based on the voltage source at node Tm.

The source at node Tm defines the scaling of channel mobility temperature dependence relative to the (non-saturated) theoretical relationship:

   mu(Tj) = mu(Tn)*A*(Tn/Tj)^1.5

where Tj and Tn are the junction and nominal (room) temperatures in Kelvin, and A is the value of the source at node Tm. If A is 1.0, then exactly the theoretical 1.5-power value is used (T.H. Lee 2001).

The behavioral expression for the current in the parallel path, relative to the current in the primary path, is:

   I_rel = V(Tm)*((Tn/Tj)^1.5 - 1), when Tj < Tj_max
   otherwise I_rel = V(Tm)*((Tn/Tj_max)^1.5 - 1)

Returns an expression for a voltage source to reduce threshold voltage with increased temperature based on the voltage source at node Tv.

The source at node Tv defines the scaling of the reduction, a linear relationship to junction temperature in degrees C above nominal. (Or below, in which case the reduction becomes an increase.) T&M p. 225.

Because the effect of increased temperature is to reduce the threshold voltage, the voltage of a source using this expression is negative with temperatures above nominal. It may be more clear to picture the source developing positive voltage drop to "soak up" some of the applied Vgs with temperatures colder than nominal, which increases effective threshold voltage. See the diagrams for drift_region and channel to see how the voltage source is inserted into the gate circuit.

For PMOS, the voltage source is inverted, i.e., made positive with temperatures above normal. That's because the effect of increased temperature is always to reduce the magnitude of the threshold voltage, whether in NMOS or PMOS. A positive voltage source in series with the gate terminal of a P-channel MOSFET will make the gate more negative, thus reducing how negative the external gate terminal needs to be.

Body diode, connected from source region to drain, or to N+ epitaxial region for VDMOS:

   >-- 15 ----+
              |-
             Diode*
              |+
              |
   <-- 35 ----+

Only forward-biased diode behavior is modeled here. Reverse-bias behavior, including breakdown voltage, is modeled as leakage current in channel.

Fixed resistances surrounding the MOSFET primitive:

                +-----------------+
                | { capacitance } |
                +-----------------+
                     |    |    |
                     |    |    |
   --> 15 -- Rd ---+-+----|----|---------> 16
                   |      |    |
                   |      |    |
                   |      |    |
   --> 25 -- Rg ---|----+-+----|---------> 29
                   |    |      |
                   | Rgs_leak  |
                   |    |      |
   <-- 35 -- Rs ---|--+-+------+---------< 39
                   |  |
               +-----------+
               | { diode } |
               +-----------+

Rs vs Rd

Rd is the drain resistance, not drift resistance.

For power MOSFETS, Rs is kept from being too much of a fraction of Rd. Not only do electrons have to travel much farther in the drift region for Rd, but the light doping there (<10% of NA in p+ region) makes its resistivity much higher than that of the p+ source region for Rs. The fact that it has more cross-sectional area than the source region does not compensate much for those two factors.

Zheng Yang ("Power MOSFET," ECE442 handout) has VDMOS source plus source contact resistivity at 0.06 mOhm/cm^2, with most of that being from the contact, and drift plus substrate plus drain contact (all part of rd) being 0.41 mOhm/cm^2. (That doesn't include accumulation resistance he puts at 0.66 mOhm/cm^2 and JFET resistance at 0.19 mOhm/cm^2.) This corresponds to an rs/rd ratio of about 15%.

For UMOS, Zheng Yang has source plus contact at 0.0505 mOhm/cm^2, with the source part vanishingly small. Drift plus substrate drain contact is 0.27 mOhm/cm^2 (not including accumulation resistance he puts at 0.055 mOhm/cm^2). This corresponds to an rs/rd ratio of about 19%.

Gate Leakage

Modeling gate leakage would require integrating gate current density vs channel position (T&M pp. 297-98). Not gonna happen. The next obvious answer is to use very high value resistances, from gate to drain and gate to source, to do a rough modeling. But the problem there is that the resistances would provide a conduction path from drain to source, swamping the drain-source leakage current.

Thus a single resistance, from gate to source, is used, and no gate-drain leakage current is modeled, current at Vgs_max being a multiple of actual rated Ig_leakage to slightly compensate for log-space behavior of actual leakage vs Vgs.

Drain-gate capacitance:

   --> 16 ---------+-----------+------------+-----+
                   |           |            |     |
                   |           ^            ^     |
                   |        +-----+      +-----+  |
                ------      |  +  |      |  +  |  |
                 Cgdo   +--x| FI1 |  +--x| FI2 |  |
                ------  |   |  -  |  |   |  -  |  |   +-----+
                   |    |   +-----+  |   +-----+  |   |     |
                   |    |      ^     |      ^     +--x|+   +|--+
                   |    |      |     |      |         |  E  |  |
   --> 29 ---------+----|------+-----|------+--------x|-    |  |
                        |            |                |     |  |
                        |            +-----------+    +-----+  |
                        |                        |             |
         +------+-------|------- 210 ---+--------|-------------+
         |      |       |               |        |
         |    ------    |             +---+      |
         |     Crss     |             | R |      |
         |    ------    |             +---+      |
       +---+    |       |               |        |
       | R |   211      |           205 +--------|-------+
       +---+    |       |               |        |       |
         |      ^       |            +-----+     |    +-----+
         |   +------+   |            |  -  |     |    |  -  |
         |   |  -   |   |            |  D3 |     |    |  D2 |
         |   | VFI1 |---+            |  +  |     |    |  +  |
         |   |  +   |                +-----+     |    +-----+
         |   +------+                   |        |       |
         |      ^                       |   +--------+   |
         |      |     +------+          +-->|+ VFI2 -|>--+ 204
         +------+---->|- D4 +|>---------+   +--------+
            206       +------+          |
                                        0

Adapted from App. Note AND9033, On Semiconductor.

Conventional current flow: v#branch is + if current ENTERS its + terminal, i.e., making its + terminal more positive.

Lightly doped drift region, which adds quasi-saturation and Vgs-independent current limiting behavior (separate velocity saturation) to power MOSFETs.

Modeled with a behavioral voltage source for accumulation region, a JFET for quasi-saturation, an inner current feedback path for mobility reduction with increased temperature, and an outer current feedback path for velocity saturation:

            +--------+          +--------+
   16 --+-->|+ Vsh1 -|>-----+-->|+ Vsh2 -|>------------- 17 -----+
        |   +--------+      |   +--------+                       |
        |       |          167     |                             V
        ^       |           |      |        +--------+   291  +------+
   29 --|-------|-----------|------|-------x| B:dVt +|-------x| B:Ra |
        |       |           |      |        |       -|--+     |      |
        |       |           |      |        +--------+  |     +------+
        |       |           V      x              x     0         V
        |       |           |   +---------+       |               |
        |       |           +-->| B:Itemp |>--+   |               |
        |       |               +---------+   |   |    +----+  18 |
        |       |                      x      +--------| Rp |-----+
        |       x                      |      |   |    +----+     |
        |   +--------+               +-|---<--+   |               V
        +--<| B:Isat |<--+           | +----------+          +--------+
            +--------+   |           |            |          |    D   |
                 x       |   +-----+ | 391 +---+  |  392     |        |
   39 -----------|-------|--x| E  +|-|-----| R |--|----+----x|G  JFET |
                 |       +--x| x1 -|-+     +---+  |    |     |        |
                 |       |   +-----+ |            |  +---+   |    S   |
                 |       |           |            |  | C |   +--------+
   Tj -----------+-------|-----------|------------+  +---+        V
                         |           |                 |          |
                         |           |                 |          |
   19 -------------------+-----------+-----------------+----------+

Note: There really is supposed to be a negative sign at the output of the zero-volt shunts. This is consistent with the Ngspice convention for a current-controlled source: "The direction of positive controlling current flow is from the positive node, through the [voltage] source, to the negative node" (4.2.4).

The idea behind the JFET is that excessive voltage V(19,39) across the intrinsic MOSFET channel will raise the JFET's source voltage with respect to its gate voltage, reducing its Vgs. That will drop more voltage across the JFET in compensation.

Adds the following parameters:

• m_aK: Accumulation effect of gate voltage reducing Ra. One plus twice the square of m_aK is how much the average gate voltage (minus m_aV), referenced to the midpoint of the accumulation region (Vga), reduces Ra.
• m_aR: Zero-bias drift region resistance Ra in the accumulation region, between the channel and JFET region, in Ohms. This will typically be much higher than Rds_on; the accumulation of electrons in the lightly doped drift region under the gate (Vga) causes it to be much more conductive when it is under a gate voltage at which Rds_on is rated.
• m_aV: Threshold gate-source voltage at which accumulation effect begins. Vga at or below this has no effect. (Depletion perhaps should be modeled, but isn't.)
• m_dB: Scaling up or down of JFET's nominal Beta value, given the computed Kp. The (somewhat implausible) lower limit of zero equals no JFET effect at all, with all the current going through the parallel resistance defined by m_dR.
• m_dI: Maximum (velocity saturated) Ids, regardless of Vgs.
• m_dL: JFET LAMBDA parameter, relative to the intrinsic MOSFET's m_kappa channel-length modulation parameter.
• m_dR: Drain region resistance Rp in parallel with and unaffected by JFET behavior. Relative to Rds_on. For a vertical architecture with no JFET effect, i.e., trench VMOS, this region is still present and the parameter has an effect.
• m_dV: Scaling up or down of JFET's nominal VTO value, given the maximum Ids.

With tempsens enabled for temperature sensitivity, the following is also defined:

• T_drm: Scaling of drift region mobility temperature dependence relative to non-saturated theoretical with 1.5 power.
• T_drv: Coefficient for linear accumulation threshold voltage decrease with higher temperature.

See, Robert S. Scott, Garhard A. Franz, and Jennifer L. Johnson (1991); Canzhong He, James Victory, et al. (2017).

For temperature dependence of semiconductor saturation velocity, R. Quay, C. Moglestue, et al. (2000).

Drain-source current through the channel, modeled with a Level 3 MOSFET primitive and parallel current source modeling temperature sensitivity:

            +------+
   19 --+-->| Vsh3 |>-- 191 --------------------------------+------+
        |   +------+                                        |      |
        |       |                                           |   +----+
        |       x                                           |   | Rp |
        |   +----------+                                    |   +----+
        +-->|+ B:temp -|>--+                                V      |
            +----------+   |                          +---------+  |
                  x        |                          |     D   |  |
                  |        |   +---------+            |         |  |
   29 ------------|--------|-->|+ B:dVt -|>-- 292 ---x|G   MOS3 |  |
                  |        |   +---------+            |         |  |
                  |        |        x                 |     S   |  |
                  |        |        |                 +---------+  |
   Tj ------------+--------|--------+                       V      |
                           |                                |      |
   39 ---------------------+--------------------------------+------+

The B-source B:dVt drops voltage on the way from the gate to the MOSFET primitive's gate terminal. Since its voltage is positive when temperature is lower than nominal, it has the effect of increasing threshold of a cold device. It has negative voltage when temperature is warming than nominal, effectively decreasing threshold of a hot device.

An ideal voltage-mode B-source has zero impedance, so the capacitance modeled by the MOS3 primitive from node 292 to nodes 191 and 39 will still be "seen" at node 29.

The B-source B:temp adjusts the total channel current based on tj to model (1) the reduction in mobility with temperature, and (2) the increase in leakage current with temperature.

Rp sets a floor for drain-source leakage current. Still included (for SCA), but only as a very high fixed value, if my has_Rp property is not True.

Call this to construct a circuit with all my stuff.