Known subclasses: pingspice.lib.mosfets.FQP32N20C_Finder, pingspice.lib.mosfets.IRF9Z34NPbF_Finder, pingspice.lib.mosfets.IXT26P20_Finder, pingspice.lib.mosfets.IXTH130N10T_Finder, pingspice.lib.mosfets.PSMN9R5_100PS_Finder, pingspice.lib.mosfets.RFP12N10L_Finder, pingspice.lib.mosfets.ST75NF20_Finder, pingspice.lib.mosfets.STP60NF06_Finder, pingspice.test.analysis.test_mosfet.MOSFET_Finder

I am a parameter finder for all MOSFETs, hopefully flexible enough that the only subclassing you need to do is to change my Setups attribute to your own subclass of MOSFET_Setups.

Here is the general progression of node numbering from the package leads to the MOSFET primitives:

    drain -> 11 -> 15 -> 17 -> 19
     gate -> 21 -> 25 -> 27 -> 29
   source -> 31 -> 35 -------> 39

Instance Variable	s	An instance that I construct of the `MOSFET_Setups` subclass referenced in your subclass of me with the Setups class attribute.
Class Variable	Setups	The subclass of `MOSFET_Setups` that your subclass uses.
Class Variable	L_tfr	Conservatively estimated series inductance (H) of a test fixture resistor plus connecting conductors. See https://www.edn.com/design/components-and-packaging/4423492/Resistors-aren-t-resistors. Also, per Marc Thompson (Intuitive Analog Circuit Design, p. 419), 10 nH per cm of lead length, over a ground plane.
Method	ao	Undocumented
Method	sc_leads	Setup circuit: Package lead impedances, plus power dissipation measurement using resistive portions of those impedances:
Method	setup	My circuit setup method, which constructs the overall MOSFET model circuit by constructing an instance of `MOSFET_Model` and calling its `MOSFET_Model.setup` method.
Method	R	A slightly more realistic test fixture resistor, with a small amount of parasitic inductance from the connecting conductors and the resistance material itself.
Method	stc_211	Setup 211: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg)
Method	stc_212	Setup 212: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg)
Method	stc_213	Setup 213: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg), non-nominal Tj.
Method	stc_220	Setup 220: Ids (-Ids) vs Vgs (Vsg) with fixed Vds (Vsd)
Method	stc_221	Setup 221: Ids (-Ids) vs Vgs (Vsg) with fixed Vds (Vsd)
Method	stc_222	Setup 222: Just like `stc_221`.
Method	stc_223	Setup 223: Rds vs Ids.
Method	stc_231	Setup 231: Body diode, forward-bias current -Ids vs -Vds. For PMOS, Ids vs -Vsd.
Method	stc_241	Setup 241: Body diode, forward-bias voltage -Vds vs -Vdd after a known resistance R. For PMOS, Vds vs Vdd.
Method	stc_242	Setup 242: Vds after drain resistor vs Vgs in weak and moderate inversion.
Method	stc_261	Setup 261: Body diode, reverse-bias current Ids vs Vds with one or more junction temperatures tj. For PMOS, Isd & Vsd.
Method	stc_262	Setup 262: Body diode, reverse-bias current Ids vs junction temperature tj with one or more Vds. For PMOS, Isd & Vsd.
Method	stc_271	Setup 271: Normalized on-state Rds vs junction temperature tj with fixed Vgs and Ids. For PMOS, fixed -Vgs & -Ids.
Method	stc_272	Setup 272: Normalized Vgs with gate shorted to drain to achieve a fixed Ids vs junction temperature tj. For PMOS, fixed -Ids.
Method	stc_321	Setup 321: Gate charge.
Method	stc_331	Setup 331: Switching times.
Method	stc_341	Setup 341: Reverse recovery time (body diode).
Method	stc_351	Setup 351: Turn-on, fast, with measurements from an actual device.
Method	stc_361	Setup 361: Turn-on, slow, with measurements from an actual device. See `stc_351`.
Method	stc_371	Setup 371: Vgs, TRAN, with measurements from an actual device.
Method	stc_411	Setup 411: Ciss, dynamically measured with sinusioid and bias on drain using an `AC_Current_Meter` subcircuit:
Method	stc_421	Setup 421: Coss, dynamically measured with biased sinusioid:
Method	stc_431	Setup 431: Crss, dynamically measured with biased sinusioid:
Method	setupTestCircuit	Sets up the test circuit for the specified setup ID during parameter finding.
Method	_checkTestConditions	Called by `stc_321`, `stc_331`, and `stc_341` to ensure that this device's test conditions have been specified for this setup ID.
Method	_drainCircuit	Undocumented

Inherited from ParameterFinder:

Method	__init__	There are two different call patterns. One is for using Differential Evolution to find parameter values:
Method	__getattr__	Looks to my subcircuit "parent" and then my `Setups` object s for attributes that I lack.
Method	tableSources	Called by `analyzerPrep` for each setup ID to possibly generate one or more TABLE sources.
Method	analyzerPrep	Call this with a setup ID to provide what the `Analyzer` for that setup will need when it is activated.
Method	__call__	Call this to find best-fit alterable values for the circuit you've defined with your `setup` override method.
Class	_EmptySetups	Undocumented
Method	__init_pf	My constructor calls this to do the full initialization in paramfinding mode, when no parameters are supplied.

s =

An instance that I construct of the MOSFET_Setups subclass referenced in your subclass of me with the Setups class attribute.

Setups =

The subclass of MOSFET_Setups that your subclass uses.

L_tfr =

Conservatively estimated series inductance (H) of a test fixture resistor plus connecting conductors. See https://www.edn.com/design/components-and-packaging/4423492/Resistors-aren-t-resistors. Also, per Marc Thompson (Intuitive Analog Circuit Design, p. 419), 10 nH per cm of lead length, over a ground plane.

@property
def ao(self):

Undocumented

def sc_leads(self, f):

Setup circuit: Package lead impedances, plus power dissipation measurement using resistive portions of those impedances:

    drain -> 11 -> 15 |
     gate -> 21 -> 25 |
   source -> 31 -> 35 |
                      +-- pdiss

Lead inductances can cause simulation trouble even though they're small, because they create high transient voltages at very high frequencies, probably a lot higher than you're interested in. If ts (time step) is set, either in my spec/subclass/instance or globally, the inductors will be simulation-friendly with parallel capacitance and resistance added to mitigate that.

ON Semiconductor's Application Note AN-6099 says, "Industry standard through-hole type TO-220 package has 7nH of typical lead inductance, but typical lead inductance of PQFN56 SMD package is only 1nH." Parameter finding of a few MOSFETs with TO220 and TO247 packages has come up with drain inductance ld values in that range, perhaps a bit lower, and lgs_vs_ld (a multiple of drain inductance for gate and source inductance, modeling the different connection those terminals make to the semiconductor die) of up to 3x or more, which seems a bit unrealistic.

Inductance will be omitted if there is a 'transient' item set in the spec's 'disabled' dict.

def setup(self, f):

overrides pingspice.analysis.param.ParameterFinder.setup

My circuit setup method, which constructs the overall MOSFET model circuit by constructing an instance of MOSFET_Model and calling its MOSFET_Model.setup method.

def R(self, f, n1, n2, resistance):

A slightly more realistic test fixture resistor, with a small amount of parasitic inductance from the connecting conductors and the resistance material itself.

def stc_211(self, f, Tj=None):

Setup 211: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg)

def stc_212(self, f):

Setup 212: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg)

def stc_213(self, f):

Setup 213: Ids (-Ids) vs Vds (Vsd), Vgs (Vsg), non-nominal Tj.

def stc_220(self, f, V=None):

Setup 220: Ids (-Ids) vs Vgs (Vsg) with fixed Vds (Vsd)

def stc_221(self, f, V=None):

Setup 221: Ids (-Ids) vs Vgs (Vsg) with fixed Vds (Vsd)

def stc_222(self, f):

Setup 222: Just like stc_221.

def stc_223(self, f):

Setup 223: Rds vs Ids.

def stc_231(self, f):

Setup 231: Body diode, forward-bias current -Ids vs -Vds. For PMOS, Ids vs -Vsd.

def stc_241(self, f):

Setup 241: Body diode, forward-bias voltage -Vds vs -Vdd after a known resistance R. For PMOS, Vds vs Vdd.

def stc_242(self, f):

Setup 242: Vds after drain resistor vs Vgs in weak and moderate inversion.

def stc_261(self, f):

Setup 261: Body diode, reverse-bias current Ids vs Vds with one or more junction temperatures tj. For PMOS, Isd & Vsd.

def stc_262(self, f):

Setup 262: Body diode, reverse-bias current Ids vs junction temperature tj with one or more Vds. For PMOS, Isd & Vsd.

def stc_271(self, f):

Setup 271: Normalized on-state Rds vs junction temperature tj with fixed Vgs and Ids. For PMOS, fixed -Vgs & -Ids.

def stc_272(self, f):

Setup 272: Normalized Vgs with gate shorted to drain to achieve a fixed Ids vs junction temperature tj. For PMOS, fixed -Ids.

def _checkTestConditions(self, ID):

Called by stc_321, stc_331, and stc_341 to ensure that this device's test conditions have been specified for this setup ID.

def stc_321(self, f):

Setup 321: Gate charge.

Adapted from test circuit in ST Datasheet, STB75NF20, STP75NF20 - STW75NF20, Figure 16 ("Gate charge test circuit")

def stc_331(self, f):

Setup 331: Switching times.

def stc_341(self, f):

Setup 341: Reverse recovery time (body diode).

def _drainCircuit(self, f, params):

Undocumented

def stc_351(self, f, ID=351):

Setup 351: Turn-on, fast, with measurements from an actual device.

Control voltage ramps up to short analog switches and hasten charging, then ramps down to restore analog switches to desired resistance.

def stc_361(self, f):

Setup 361: Turn-on, slow, with measurements from an actual device. See stc_351.

def stc_371(self, f):

Setup 371: Vgs, TRAN, with measurements from an actual device.

def stc_411(self, f):

Setup 411: Ciss, dynamically measured with sinusioid and bias on drain using an AC_Current_Meter subcircuit:

                                                   +--------+
                                                   |        |
   +---------------+              +---<-- C --+---<|D <\    |
   |               |              |           |    |   ^    |
   |          npos |>-- 'gate' ---|--->-------|--->|G >X    |
   |           :   |              |           |    |   V    |
   |   CM.sB   :   |              V           |    |   V    |
   |           :   |              |           |    |   V    |
   |    +---< nneg |<-- 'source'--+---<-------|---<|S </    |
   |    |          |                          |    |        |
   |    0          |                          |    +--------+
   |               |                          |
   |          bias |>---- R -- 'drain' -------+
   |               |                          |
   |           cap |>-------------------------|-------: 'cap1'
   |               |                          |
   |       filt_in |<-------------------------+
   |               |
   |      filt_out |>---------------------------------: 'bias1'
   |               |
   +---------------+

B-source B:current calculates the current flowing through R and adds it to current0 to generate the final output voltage at node current.

There is some tension with the values of R and C. The value of C has to be significantly higher than the MOSFET's Cgd. The value of R has to be low enough, in combination with C, that the RC time constant (to charge C as bias increases) is significantly less than the ramp-up time of the bias voltage. But the lower R is, the more AC current will leak through it back to the bias source instead of being measured.

In order to keep R high, a relatively high time constant is tolerated and the bias output of CM is overdriven.

def stc_421(self, f):

Setup 421: Coss, dynamically measured with biased sinusioid:

   +-----------------+                   +--------+
   |                 |                   |        |
   |  +--(+)--> npos |>-------->-------->|D >\    |
   |  |          :   |                   |   V    |
   |  |          :   |           +------<|G <X    |
   |  |          :   |           |       |   V    |
   |  |    +--< nneg |<-----<----+       |   V    |
   |  |    |         |           |       |   V    |
   |  |    0         |           +------<|S </    |
   |  |              |                   |        |
   |  |   CM.aB      |                   +--------+
   |  |              |
   |  +-------< bias |>---+
   |                 |    |
   |             cap |>---|-----------------------------: 'cap1'
   |                 |    |
   |         filt_in |<---+
   |                 |
   |        filt_out |>---------------------------------: 'bias1'
   |                 |
   +-----------------+

Leakage current from the DC bias at the drain could affect capacitance measurement, but should be very small.

def stc_431(self, f):

Setup 431: Crss, dynamically measured with biased sinusioid:

   +-----------------+                   +--------+
   |                 |                   |        |
   |  +--(+)--> npos |>-------->-------->|D >\    |
   |  |          :   |                   |   V    |
   |  |          :   |           +------<|G <X    |
   |  |          :   |           |       |   V    |
   |  |    +--< nneg |<-----<----+       |   V    |
   |  |    |         |                   |   V    |
   |  |    0         |             +----<|S </    |
   |  |              |             |     |        |
   |  |   CM.aB      |             0     +--------+
   |  |              |
   |  +-------< bias |>---+
   |                 |    |
   |             cap |>---|-----------------------------: 'cap1'
   |                 |    |
   |         filt_in |<---+
   |                 |
   |        filt_out |>---------------------------------: 'bias1'
   |                 |
   +-----------------+

Leakage current from the DC bias at the drain could affect capacitance measurement, but should be very small.

def setupTestCircuit(self, f, ID):

overrides pingspice.analysis.param.ParameterFinder.setupTestCircuit

Sets up the test circuit for the specified setup ID during parameter finding.

Increases my ts sim option to the computational timestep of this setup's transient analysis if needed to make simulation-friendly components work.

For all setups but the capacitance measurements, source is tied to ground.

API Documentation for pingspice, generated by pydoctor at 2021-09-18 08:41:11.

pingspice.analysis.mosfet.MOSFET_Finder(param.ParameterFinder) class documentation

`pingspice.analysis.mosfet.MOSFET_Finder(param.ParameterFinder)` class documentation